Smart Cache: An Energy-Efficient D-Cache for a Software MPEG-2 Video Decoder

Power consumption is an important design issue of c ~ e n r embedded systems. Data caches consume a signifcant portion of total processor power for data intensive applications. In this p w we propose to utili-e application-specifc information for cache resotrrce allocntion to achieve energv saving, including cache bypassing, the mini-cache and way-pmrition. We use a sopVare MpEG-2 video decoder as our jimt t q e t e d application. Cache bypassing acludes data tpes that have little m e from the L1 cache. The mini-cache stores data tpes with high access frequency and small memory footprints to a small on-chip memory area The wq-partition mechanism m a p pmgram data struchues to different ways of caches and enables only the matching ways on each access. The results show up to 40% of cache energy reduction without sacri3cing pdormance.